Among the more salient accelerator technologies to continue performance scaling in High-Performance Computing (HPC) are Coarse-Grained Reconfigurable Arrays (CGRAs). However, what benefits CGRAs will bring to HPC workloads and how those benefits will be reaped is an open research question today. In this work, we propose a framework to explore the design space of CGRAs for HPC workloads, which includes a tool flow of compilation and simulation, a CGRA HDL library written in SystemVerilog, and a synthesizable CGRA design as a baseline. Using RTL simulation, we evaluate two well-known computation kernels with the baseline CGRA for multiple different architectural parameters. The simulation results demonstrate both correctness and usefulness of our exploration framework.