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Network Monitoring on Multi-Pipe Switches
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS, Network Systems Laboratory (NS Lab).ORCID iD: 0000-0002-9675-9729
Fed Univ Sao Carlos UFSCar, Rod Joao Leme dos Santos,Km 110, BR-18052780 Sorocaba, Brazil..
2023 (English)In: PROCEEDINGS OF THE ACM ON MEASUREMENT AND ANALYSIS OF COMPUTING SYSTEMS, ISSN 2476-1249, Vol. 7, no 1, p. 1-31, article id 3-ART8Article in journal (Refereed) Published
Abstract [en]

Programmable switches have been widely used to design network monitoring solutions that operate in the fast data-plane level, e.g., detecting heavy hitters, super-spreaders, computing flow size distributions and their entropy. Many existing works on networking monitoring assume switches deploy a single memory that is accessible by each processed packet. However, high-speed ASIC switches increasingly deploy multiple independent pipes, each equipped with its own independent memory that cannot be accessed by other pipes. In this work, we initiate the study of deploying existing heavy-hitter data-plane monitoring solutions on multi-pipe switches where packets of a "flow" may spread over multiple pipes, i.e., stored into distinct memories. We first quantify the accuracy degradation due to splitting a monitoring data structure across multiple pipes (e.g., up to 3000xworse flow-size estimation average error). We then present PipeCache, a system that adapts existing data-plane mechanisms to multi-pipe switches by carefully storing all the monitoring information of each traffic class into exactly one specific pipe (as opposed to replicate the information on multiple pipes). PipeCache relies on the idea of briefly storing monitoring information into a per-pipe cache and then piggybacking this information onto existing data packets to the correct pipe entirely at data-plane speed. We implement PipeCache on ASIC switches and we evaluate it using a real-world trace. We show that existing data-plane mechanisms achieves accuracy levels and memory requirements similar to single-pipe deployments when augmented with PipeCache (i.e., up to 16x lower memory requirements).

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM) , 2023. Vol. 7, no 1, p. 1-31, article id 3-ART8
Keywords [en]
multi-pipe switches, ASIC switches, network monitoring, P4
National Category
Communication Systems Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-325594DOI: 10.1145/3579321ISI: 000942440100006Scopus ID: 2-s2.0-85149860859OAI: oai:DiVA.org:kth-325594DiVA, id: diva2:1750085
Funder
Swedish Research Council, 2021-04212
Note

QC 20230508

Available from: 2023-04-12 Created: 2023-04-12 Last updated: 2023-05-08Bibliographically approved

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Chiesa, Marco

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CiteExportLink to record
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  • apa
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