Inspired by PiN, Processing in Network-on-Chip (NoC), we propose a computational NoC as a convolution engine for accelerating convolutional neural networks in hardware. In contrast to traditional compute architectures where computation and communication are conducted serially and in separation, our computational NoC enables in-transit computation, meaning that computation is performed while packets are transferred in the network. In the paper, we present the router architecture that supports the novel in-transit computation concept, and use a running example to detail the entire convolution process in the computational NoC. Finally, we show simulated performance results in comparison with traditional NoC-based convolution engine.