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A Frequency Synthesizer Architecture Using Frequency Difference Detection
KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
Tottori Kankyo University, Dept. of Information Systems, 1-1 Wakabadai-Kita, Tottori, 689-1111 Japan, 1-1 Wakabadai-Kita.
KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments (pre-2005), Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0003-1959-6513
2003 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2003. p. 1155-1157
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-350624DOI: 10.1109/MWSCAS.2003.1562498Scopus ID: 2-s2.0-85150720740OAI: oai:DiVA.org:kth-350624DiVA, id: diva2:1884522
Conference
46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003, Cairo, Egypt, Dec 27 2003 - Dec 30 2003
Note

Part of ISBN 0780382943

QC 20240717

Available from: 2024-07-17 Created: 2024-07-17 Last updated: 2024-07-17Bibliographically approved

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Albrecht, SteffenTenhunen, Hannu

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