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Work-in-Progress: Exploring Limited Preemption Approaches for the Phased Execution Model
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0001-9363-3525
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-1276-3609
2024 (English)In: Proceedings - 2024 IEEE Real-Time Systems Symposium, RTSS 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 447-450Conference paper, Published paper (Refereed)
Abstract [en]

Phased execution models separate computation from access to shared resources to make task execution predictable. These task models minimize interference between tasks, making them suitable for modern complex multi-core platforms. In the phased execution model, tasks perform computations only using the local memory to avoid accessing the shared memory during task execution. All instructions and data, including the intermediate results, are stored in the local memory during execution. Thus, the local memory size becomes a crucial factor in contrast to conventional execution. In the literature, non-preemptive and fully preemptive execution of phased execution models are studied. While the non-preemptive approaches utilize the local memory well, schedulability is reduced due to blocking. On the other hand, fully preemptive execution phases allow for better schedulability but require significantly more local memory capacity to implement preemptions at runtime without violating the model's execution semantics. Thus, this work evaluates different approaches to limited preemptive scheduling of the phased execution model under partitioned fixed-priority scheduling. We demonstrate that preemption thresholds and non-preemptive regions can successfully be used to satisfy both timing and memory constraints of phased tasks.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024. p. 447-450
Keywords [en]
multi-core, phased execution model, preemption
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-360167DOI: 10.1109/RTSS62706.2024.00048Scopus ID: 2-s2.0-85217618621OAI: oai:DiVA.org:kth-360167DiVA, id: diva2:1938784
Conference
45th IEEE Real-Time Systems Symposium, RTSS 2024, York, United Kingdom of Great Britain and Northern Ireland, Dec 10 2024 - Dec 13 2024
Note

Part of ISBN 9798331540265

QC 20250220

Available from: 2025-02-19 Created: 2025-02-19 Last updated: 2025-02-20Bibliographically approved

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Thilakasiri, ThilankaBecker, Matthias

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