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FDSOI CMOS failure mechanism at high process and operating temperature
KTH, School of Electrical Engineering and Computer Science (EECS).
2025 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesisAlternative title
FDSOI CMOS-felmekanism vid hög process- och arbetstemperatur (Swedish)
Abstract [en]

Silicon-based MOSFETs for high-temperature applications face inherent limitations, primarily due to increased P-N junction leakage currents as the operating temperature rises. Employing more advanced architectures, such as FDSOI CMOS, can mitigate this issue. At KTH, transistors featuring this architecture, TiW metallization, and gold bond pads were fabricated for high temperature operation. Furthermore, this thesis evaluates their performance and investigates the failure mechanisms of the devices at their limiting temperature of 500 ◦C. During short term high temperature exposure, the transistors exhibited an on and off state, with ideal values of Vth and Iof f up to 500 ◦C, and ideal SS up to 300 ◦C. After annealing the sample for 50 hours at 500 ◦C, it was found that the main failure mechanism is related to material degradation within the bond pad stack rather than the transistor itself. The bond pads exhibited cracks and delamination at their interfaces due to a mismatch in the coefficient of thermal expansion between materials and oxygen diffusion.

Abstract [sv]

Kiselbaserade MOSFET:ar för högtemperaturtillämpningar har inneboende begränsningar, främst på grund av ökade läckströmmar i P-N-övergången vid stigande arbetstemperaturer. Användningen av mer avancerade arkitekturer, såsom FDSOI CMOS, kan minska dessa problem. Vid KTH tillverkades transistorer med denna arkitektur, TiW-metallisering och guldbondpads för högtemperaturdrift. I denna avhandling utvärderas deras prestanda och felmekanismerna i enheterna vid deras gränstemperatur på 500 ◦C undersöks. Under kortvarig exponering för höga temperaturer uppvisade transistorerna både på- och av-läge med ideala värden för Vth och Iof f upp till 500 ◦C samt ideal SS upp till 300 ◦C. Efter 50 timmars anlöpning vid 500 ◦C konstaterades att den huvudsakliga felmekanismen är relaterad till materialdegradering i bondpadstacken snarare än i själva transistorn. Bondpadsen visade sprickbildning och delaminering vid gränsskikten, vilket berodde på en mismatch i de termiska expansionskoefficienterna mellan materialen samt syrgasdiffusion.

Place, publisher, year, edition, pages
2025. , p. 67
Series
TRITA-EECS-EX ; 2025:19
Keywords [en]
Fully Depleted Silicon on Insulator, Failure analysis, High temperature operation, Reliability, Gold bond pads.
Keywords [sv]
Fullständigt utarmad kisel på isolator, felfallsanalys, högtemperaturdrift, tillförlitlighet, guldbondpads.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-361688OAI: oai:DiVA.org:kth-361688DiVA, id: diva2:1947319
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Available from: 2025-03-31 Created: 2025-03-25 Last updated: 2025-03-31Bibliographically approved

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CiteExportLink to record
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