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Energy and Design Cost Efficiency for Streaming Applications on Systems-on-Chip
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. (SAM)
2009 (English)Licentiate thesis, monograph (Other academic)
Abstract [en]

With the increasing capacity of today's integrated circuits, a number ofheterogeneous  system-on-chip (SoC)  architectures  in embedded  systemshave been proposed. In order to achieve energy and design cost efficientstreaming applications  on these  systems, new design  space explorationframeworks  and  performance  analysis  approaches are  required.   Thisthesis  considers three state-of-the-art  SoCs architectures,  i.e., themulti-processor SoCs (MPSoCs)  with network-on-chip (NoC) communication,the hybrid CPU/FPGA architectures, and the run-time reconfigurable (RTR)FPGAs.  The main topic of the  author?s research is to model and capturethe  application  scheduling,  architecture  customization,  and  bufferdimensioning  problems, according to  the real-time  requirement.  Sincethese  problems  are NP-complete,  heuristic  algorithms and  constraintprogramming solver are used to compute a solution.For  NoC  communication  based  MPSoCs,  an  approach  to  optimize  thereal-time    streaming    applications    with   customized    processorvoltage-frequency levels and memory  sizes is presented. A multi-clockedsynchronous  model  of  computation   (MoC)  framework  is  proposed  inheterogeneous  timing analysis and  energy estimation.   Using heuristicsearching  (i.e., greedy  and  taboo search),  the  experiments show  anenergy reduction (up to 21%)  without any loss in application throughputcompared with an ad-hoc approach.On hybrid CPU/FPGA architectures,  the buffer minimization scheduling ofreal-time streaming  applications is addressed.  Based  on event models,the  problem  has  been  formalized  decoratively  as  constraint  basescheduling,  and  solved  by  public domain  constraint  solver  Gecode.Compared  with  traditional  PAPS  method,  the  proposed  method  needssignificantly smaller  buffers (2.4%  of PAPS in  the best  case), whilehigh throughput guarantees can still be achieved.Furthermore, a  novel compile-time analysis approach  based on iterativetiming  phases is  proposed  for run-time  reconfigurations in  adaptivereal-time   streaming   applications  on   RTR   FPGAs.   Finally,   thereconfigurations analysis and design trade-offs analysis capabilities ofthe proposed  framework have been  exemplified with experiments  on bothexample and industrial applications.

Place, publisher, year, edition, pages
Stockholm: Universitetsservice US AB , 2009. , xii, 67 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 09:02
Keyword [en]
Streaming applications, Systems-on-chip, Synchronous dataflow, energy efficiency, buffer minimization, performance analysis
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-10591ISBN: 978-91-7415-306-4OAI: diva2:220403
2009-05-25, Sal D KTH-Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Available from: 2009-06-08 Created: 2009-06-01 Last updated: 2010-11-03Bibliographically approved

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