Change search
ReferencesLink to record
Permanent link

Direct link
Flit ejection in on-chip wormhole-switched networks with virtual channels
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-0061-3475
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, IEEE conference proceedings, 2004, 273-276 p.Conference paper (Refereed)
Abstract [en]

An ideal it-ejection model is typically assumed in the literature for wormhole switches with virtual channels. With such a model, its are ejected from the network immediately upon reaching their destinations. This achieves optimal performance but is very costly. The required number of sink queues of a switch for absorbing its is p center dot v, where p is the number of physical channels (PCs) of the switch; v the number of lanes per PC To achieve cheap silicon implementations, it-ejection solutions must be cost-effective. We present a novel it-ejection model and a variant of it where the required number of sink queues of a switch is p, i.e., independent of v. We evaluate the it-ejection models with uniformly distributed random traf c in a 2D mesh network. Experimental results show that they exhibit good performance in latency and throughput.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2004. 273-276 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-13037DOI: 10.1109/NORCHP.2004.1423876ISI: 000227801500068ScopusID: 2-s2.0-21244435987OAI: diva2:320315
IEEE NorChip Conference, Oslo, Norway, November 2004.

QC 20100524. QC 20160212

Available from: 2010-05-24 Created: 2010-05-24 Last updated: 2016-02-12Bibliographically approved
In thesis
1. Using wormhole switching for networks on chip: feasibility analysis and microarchitecture adaptation
Open this publication in new window or tab >>Using wormhole switching for networks on chip: feasibility analysis and microarchitecture adaptation
2005 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

Network-on-Chip (NoC) is proposed as a systematic approach to address future System-on-Chip (SoC) design difficulties. Due to its good performance and small buffering requirement, wormhole switching is being considered as a main network flow control mechanism for on-chip networks. Wormhole switching for NoCs is challenging from NoC application design and switch complexity reduction.

In a NoC design flow, mapping an application onto the network should conduct a feasibility analysis in order to determine whether the messages’ timing constraints can be satisfied, and whether the network can be efficiently utilized. This is necessary because network contentions lead to nondeterministic behavior in message delivery. For wormhole-switched networks, we have formulated a contention tree model to accurately capture network contentions and reflect the concurrent use of links. Based on this model, the timing bounds of real-time messages can be derived. Furthermore, we have developed an algorithm to test the feasibility of real-time messages in the networks.

From the wormhole switch micro-architecture level, switch complexity should be minimized to reduce cost but with reasonable performance penalty. We have investigated the flit admission and flit ejection problems that concern how the flits of packets are admitted into and ejected from the network, respectively. For flit admission, we propose a novel coupling scheme which binds a flit-admission queue with an output physical channel. Our results show that this scheme achieves a reduction of up to 8% in switch area and up to 35% in switch power over other comparable solutions. For flit ejection, we propose a p-sink model which differs from a typical ideal ejection model in that it uses only p flit sinks to eject flits instead of p • v flit sinks as required by the ideal model, where p is the number of physical channels of a switch and v is the number of virtual channels per physical channel. With this model, the buffering cost of flit sinks only depends on p, i.e., is irrespective of v. We have evaluated the coupled flit-admission technique and p-sink model in a 2D 4 x 4 mesh network. In our experiments, they exhibit only limited performance penalties in some cases. We believe that these cost-effective models are promising candidates to be used in wormhole-switched on-chip networks.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. x, 46 p.
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:5
National Category
Engineering and Technology
urn:nbn:se:kth:diva-562 (URN)
QC 20100524Available from: 2005-12-28 Created: 2005-12-28 Last updated: 2012-03-23Bibliographically approved
2. Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
Open this publication in new window or tab >>Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement.

Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions.

Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage.

In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput.

The thesis summarizes the major research results on the three topics.

Place, publisher, year, edition, pages
Stockholm: KTH, 2007. xvi, 109 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 2007:02
On-Chip Communication, Network-on-Chip, System-on-Chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
urn:nbn:se:kth:diva-4290 (URN)978-91-7178-580-0 (ISBN)
Public defence
2007-03-15, D, KTH Forum, Isafördsgatan 39, Kista, 13:00 (English)
QC 20100525Available from: 2007-02-28 Created: 2007-02-28 Last updated: 2010-08-06Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Lu, ZhonghaiJantsch, Axel
By organisation
Electronic Systems Design
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 44 hits
ReferencesLink to record
Permanent link

Direct link