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Connection-oriented multicasting in wormhole-switched networks on chip
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2006 (English)In: IEEE Computer Society Annual Symposium on VLSI, Proceedings - EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, 205-210 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting. As the system size scales up to explore the chip capacity, broadcasting in NoCs must be efficiently supported. This paper presents a novel multicast scheme in wormhole-switched NoCs. By this scheme, a multicast procedure consists of establishment, communication and release phase. A multicast group can request to reserve virtual channels during establishment and has priority on arbitration of link bandwidth. This multicasting method has been effectively implemented in a mesh network with dead-lock freedom. Our experiments show that the multicast technique improves throughput, and does not exhibit significant impact on unicast performance in a network with mixed unicast and multicast traffic if the network is not saturated.

Place, publisher, year, edition, pages
2006. 205-210 p.
Keyword [en]
Communication channels (information theory); Interconnection networks; Microprocessor chips; Switching networks; Telecommunication traffic; Throughput; Chip capacity; Global communication interconnect; Multicast traffic; Virtual channels; Multicasting
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-13057DOI: 10.1109/ISVLSI.2006.31ISI: 000237225200032Scopus ID: 2-s2.0-33749348991OAI: oai:DiVA.org:kth-13057DiVA: diva2:320462
Conference
ISVLSI'2006
Note

QC 20100525. QC 20160212

Available from: 2010-05-25 Created: 2010-05-25 Last updated: 2016-02-12Bibliographically approved
In thesis
1. Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
Open this publication in new window or tab >>Design and Analysis of On-Chip Communication for Network-on-Chip Platforms
2007 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. NoC problems spread in the whole SoC spectrum ranging from specification, design, implementation to validation, from design methodology to tool support. In the thesis, we formulate and address problems in three key NoC areas, namely, on-chip network architectures, NoC network performance analysis, and NoC communication refinement.

Quality and cost are major constraints for micro-electronic products, particularly, in high-volume application domains. We have developed a number of techniques to facilitate the design of systems with low area, high and predictable performance. From flit admission and ejection perspective, we investigate the area optimization for a classical wormhole architecture. The proposals are simple but effective. Not only offering unicast services, on-chip networks should also provide effective support for multicast. We suggest a connection-oriented multicasting protocol which can dynamically establish multicast groups with quality-of-service awareness. Based on the concept of a logical network, we develop theorems to guide the construction of contention-free virtual circuits, and employ a back-tracking algorithm to systematically search for feasible solutions.

Network performance analysis plays a central role in the design of NoC communication architectures. Within a layered NoC simulation framework, we develop and integrate traffic generation methods in order to simulate network performance and evaluate network architectures. Using these methods, traffic patterns may be adjusted with locality parameters and be configured per pair of tasks. We propose also an algorithm-based analysis method to estimate whether a wormhole-switched network can satisfy the timing constraints of real-time messages. This method is built on traffic assumptions and based on a contention tree model that captures direct and indirect network contentions and concurrent link usage.

In addition to NoC platform design, application design targeting such a platform is an open issue. Following the trends in SoC design, we use an abstract and formal specification as a starting point in our design flow. Based on the synchronous model of computation, we propose a top-down communication refinement approach. This approach decouples the tight global synchronization into process local synchronization, and utilizes synchronizers to achieve process synchronization consistency during refinement. Meanwhile, protocol refinement can be incorporated to satisfy design constraints such as reliability and throughput.

The thesis summarizes the major research results on the three topics.

Place, publisher, year, edition, pages
Stockholm: KTH, 2007. xvi, 109 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 2007:02
Keyword
On-Chip Communication, Network-on-Chip, System-on-Chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4290 (URN)978-91-7178-580-0 (ISBN)
Public defence
2007-03-15, D, KTH Forum, Isafördsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note
QC 20100525Available from: 2007-02-28 Created: 2007-02-28 Last updated: 2010-08-06Bibliographically approved

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Lu, Zhonghai

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