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Integration of metallic source/drain contacts in MOSFET technology
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices.

First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification.

Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology.

Place, publisher, year, edition, pages
Stockholm: KTH , 2010. , xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2010:06
Keyword [en]
CMOS technology, MOSFET, Schottky barrier MOSFET, metallic source/drain, contact resistivity, NiSi, PtSi, SALICIDE, ultrathin silicide, FinFET
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:kth:diva-13136ISBN: 978-91-7415-680-5 (print)OAI: oai:DiVA.org:kth-13136DiVA: diva2:321150
Public defence
2010-06-18, Sal C1, KTH-Electrum 1, Isafjordsgatan 22, Kista, 15:28 (English)
Opponent
Supervisors
Projects
NEMO, NANOSIL, SINANO
Note
QC20100708Available from: 2010-05-31 Created: 2010-05-28 Last updated: 2010-07-08Bibliographically approved
List of papers
1. Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation
Open this publication in new window or tab >>Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation
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2009 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6Article in journal (Refereed) Published
Abstract [en]

The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased ∅bn from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600°C. Above this temperature, B-DS at this interface is evident thus keeping φbn high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning ∅bp above 1.0 eV by As-DS.

Identifiers
urn:nbn:se:kth:diva-14021 (URN)
Note
QC20100708Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
2. Interaction of NiSi with dopants for metallic source/drain applications
Open this publication in new window or tab >>Interaction of NiSi with dopants for metallic source/drain applications
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2010 (English)In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 28, no 1, C1I1-C1I11 p.Article in journal (Refereed) Published
Abstract [en]

This work has a focus on NiSi as a possible metallic contact for aggressively scaled complementary metal oxide semiconductor devices. As the bulk work function of NiSi lies close to the middle of Si bandgap, the Schottky barrier height (SBH) of NiSi is rather large for both electron (similar to 0.65 eV) and hole (similar to 0.45 eV). Different approaches have therefore been intensively investigated in the literature aiming at reducing the effective SBH: dopant segregation (DS), surface passivation (SP), and alloying, in order to improve the carrier injection into the conduction channel of a field-effect transistor. The present work explores DS using B and As for the NiSi/Si contact system. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. A combined use of DS or SP with alloying could be considered for more effective control of effective SBH, but an examination of undesired compound formation and its probable consequences is necessary. Furthermore, an analysis of the metal silicides that have a small "intrinsic" SBH reveals that only a very small number of them are of practical interest as most of the silicides require either a high formation temperature or possess a high specific resistivity.

Keyword
alloying, carbon, charge injection, electrical resistivity, elemental semiconductors, energy gap, field effect transistors, impurity distribution, ion implantation, nickel alloys, nitrogen, passivation, Schottky barriers, segregation, silicon, silicon alloys, work function, SCHOTTKY-BARRIER HEIGHT, SILICON-CARBON SOURCE/DRAIN, SHALLOW JUNCTION FORMATION, OXIDE-SEMICONDUCTOR TECHNOLOGY, NITROGEN ION-IMPLANTATION, FIELD-EFFECT TRANSISTORS, FULLY SILICIDED GATES, N-CHANNEL MOSFETS, CONTACT TECHNOLOGY, HIGH-PERFORMANCE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-14028 (URN)10.1116/1.3248267 (DOI)000275511800013 ()2-s2.0-77949392162 (Scopus ID)
Note
QC 20110114Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
3. Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films
Open this publication in new window or tab >>Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films
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2010 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 96, no 3Article in journal (Refereed) Published
Abstract [en]

The formation of ultrathin silicide films of Ni1-xPtx at 450-850 degrees C is reported. Without Pt (x=0) and for t(Ni)< 4 nm, epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 degrees C. For t(Ni)>= 4 nm, polycrystalline NiSi films form and agglomerate at lower temperatures for thinner films. Without Ni (x=1) and for t(Pt)=1-20 nm, the annealing behavior of the resulting PtSi films follows that for the NiSi films. The results for Ni1-xPtx of other compositions support the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

Keyword
annealing, crystal morphology, metallic epitaxial layers, nanostructured materials, nickel alloys, nickel compounds, surface energy, NISI, SI, TECHNOLOGY, COSI2
National Category
Physical Sciences
Identifiers
urn:nbn:se:kth:diva-14032 (URN)10.1063/1.3291679 (DOI)000273890500024 ()2-s2.0-77949851089 (Scopus ID)
Funder
Knut and Alice Wallenberg Foundation
Note
QC20100708Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
4. Kinetics and morphology of Ni1-xPtx-silicide epitaxy on Si(001)
Open this publication in new window or tab >>Kinetics and morphology of Ni1-xPtx-silicide epitaxy on Si(001)
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(English)In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775Article in journal (Other academic) Submitted
Identifiers
urn:nbn:se:kth:diva-14033 (URN)
Note
QS 20120328Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
5. On different process schemes for a controllable NiSi-based metallic source/drainMOSFETs with dopant segregation
Open this publication in new window or tab >>On different process schemes for a controllable NiSi-based metallic source/drainMOSFETs with dopant segregation
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(English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Article in journal (Other academic) Submitted
Identifiers
urn:nbn:se:kth:diva-14034 (URN)
Note
QS 20120328Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
6. Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
Open this publication in new window or tab >>Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
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2009 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, 541-543 p.Article in journal (Refereed) Published
Abstract [en]

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

Keyword
Dopant segregation (DS), FinFET, platinum silicide PtSi, Schottky-barrier (SB)-MOSFET, trigate, YTTERBIUM SILICIDE, SOURCE/DRAIN, TECHNOLOGY
Identifiers
urn:nbn:se:kth:diva-14035 (URN)10.1109/LED.2009.2015900 (DOI)000265711700039 ()2-s2.0-67349263386 (Scopus ID)
Note
QC20100708Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2017-12-12Bibliographically approved
7. Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
Open this publication in new window or tab >>Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
Show others...
2010 (English)In: 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, 9-13 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.

Keyword
CMOS technology, Device design, Device performance, Future generations, Gate underlap, Low temperature processing, MOSFETs, Nano-scaling, Ni-silicide, Oxide thickness, Salicides, Schottky barriers, Schottky-barrier MOSFET, Schottky-barrier-height engineerings, Series resistances, Si films
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-14036 (URN)2-s2.0-77955183371 (Scopus ID)978-142447201-7 (ISBN)
Conference
2010 27th International Conference on Microelectronics, MIEL 2010; Nis; Serbia; 16 May 2010 through 19 May 2010
Note

QC 20100708

Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2014-08-26Bibliographically approved

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