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Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis
Ohio State Univ, Analog VLSI Lab.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. (RaMSiS)
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. (RaMSiS)ORCID iD: 0000-0003-3802-7834
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2010 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 18, no 2, 194-200 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a comparative study of Sigma Delta modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

Place, publisher, year, edition, pages
2010. Vol. 18, no 2, 194-200 p.
Keyword [en]
Frequency synthesizers, phase-locked loops (PLLs), phase noise, Sigma Delta modulation
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-13978DOI: 10.1109/TVLSI.2008.2009058ISI: 000273774700003ScopusID: 2-s2.0-75549083172OAI: diva2:328748
Swedish Research Council
QC 20100706. Tidigare titel: Selection of Optimal Sigma Delta Modulator Architecture for Fractional-N Frequency Synthesis.Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2011-01-27Bibliographically approved
In thesis
1. Integrated Frequency Synthesis for Convergent Wireless Solutions
Open this publication in new window or tab >>Integrated Frequency Synthesis for Convergent Wireless Solutions
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xviii, 182 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:07
wireless, transceiver, Bluetooth, DECT, GSM, 3G, LTE, WLAN, WiMAX, multi-standard, vertical handover, Sniffer, frequency synthesizer, phase-locked loop, PLL, sigma-delta, calibration
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
urn:nbn:se:kth:diva-9486 (URN)978-91-7415-142-8 (ISBN)
Public defence
2008-11-20, sal D, Forum, KTH, Isafjordsgatan 39, Kista, 14:00 (English)
QC 20100706Available from: 2008-11-10 Created: 2008-11-07 Last updated: 2010-07-06Bibliographically approved

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