Wide-Division-Range High-Speed Fully Programmable Frequency Divider
2008 (English)In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, 17-20 p.Conference paper (Refereed)
This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2008. 17-20 p.
frequency synthesizers, prescalers, high-speed integrated circuits, DUAL-MODULUS PRESCALER, CMOS TECHNOLOGY
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-13990DOI: 10.1109/NEWCAS.2008.4606310ISI: 000262463700005ScopusID: 2-s2.0-52449098048OAI: oai:DiVA.org:kth-13990DiVA: diva2:328843
Joint IEEE North-East Workshop on Circuits and Systems/TAISA Conference, Montreal, CANADA, JUN 22-25, 2008
QC 201007062010-07-062010-07-062010-07-06Bibliographically approved