Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Wide-Division-Range High-Speed Fully Programmable Frequency Divider
Ohio State Univ, Analog VLSI Lab.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-3802-7834
Show others and affiliations
2008 (English)In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, 17-20 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

Place, publisher, year, edition, pages
NEW YORK: IEEE , 2008. 17-20 p.
Keyword [en]
frequency synthesizers, prescalers, high-speed integrated circuits, DUAL-MODULUS PRESCALER, CMOS TECHNOLOGY
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-13990DOI: 10.1109/NEWCAS.2008.4606310ISI: 000262463700005Scopus ID: 2-s2.0-52449098048OAI: oai:DiVA.org:kth-13990DiVA: diva2:328843
Conference
Joint IEEE North-East Workshop on Circuits and Systems/TAISA Conference, Montreal, CANADA, JUN 22-25, 2008
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2010-07-06Bibliographically approved
In thesis
1. Integrated Frequency Synthesis for Convergent Wireless Solutions
Open this publication in new window or tab >>Integrated Frequency Synthesis for Convergent Wireless Solutions
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xviii, 182 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:07
Keyword
wireless, transceiver, Bluetooth, DECT, GSM, 3G, LTE, WLAN, WiMAX, multi-standard, vertical handover, Sniffer, frequency synthesizer, phase-locked loop, PLL, sigma-delta, calibration
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-9486 (URN)978-91-7415-142-8 (ISBN)
Public defence
2008-11-20, sal D, Forum, KTH, Isafjordsgatan 39, Kista, 14:00 (English)
Opponent
Supervisors
Note
QC 20100706Available from: 2008-11-10 Created: 2008-11-07 Last updated: 2010-07-06Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Rusu, Ana

Search in DiVA

By author/editor
Sleiman, Sleiman BouAtallah, Jad G.Rodriguez Duenas, SaulRusu, AnaElnaggar, Mohammed Ismail
By organisation
Electronic, Computer and Software Systems, ECS
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 100 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf