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Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
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2009 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, 541-543 p.Article in journal (Refereed) Published
Abstract [en]

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

Place, publisher, year, edition, pages
2009. Vol. 30, no 5, 541-543 p.
Keyword [en]
Dopant segregation (DS), FinFET, platinum silicide PtSi, Schottky-barrier (SB)-MOSFET, trigate, YTTERBIUM SILICIDE, SOURCE/DRAIN, TECHNOLOGY
Identifiers
URN: urn:nbn:se:kth:diva-14035DOI: 10.1109/LED.2009.2015900ISI: 000265711700039Scopus ID: 2-s2.0-67349263386OAI: oai:DiVA.org:kth-14035DiVA: diva2:329216
Note
QC20100708Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2011-12-06Bibliographically approved
In thesis
1. Integration of metallic source/drain contacts in MOSFET technology
Open this publication in new window or tab >>Integration of metallic source/drain contacts in MOSFET technology
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices.

First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification.

Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology.

Place, publisher, year, edition, pages
Stockholm: KTH, 2010. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2010:06
Keyword
CMOS technology, MOSFET, Schottky barrier MOSFET, metallic source/drain, contact resistivity, NiSi, PtSi, SALICIDE, ultrathin silicide, FinFET
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-13136 (URN)978-91-7415-680-5 (ISBN)
Public defence
2010-06-18, Sal C1, KTH-Electrum 1, Isafjordsgatan 22, Kista, 15:28 (English)
Opponent
Supervisors
Projects
NEMO, NANOSIL, SINANO
Note
QC20100708Available from: 2010-05-31 Created: 2010-05-28 Last updated: 2010-07-08Bibliographically approved
2. Fabrication, characterization, and modeling of metallic source/drain MOSFETs
Open this publication in new window or tab >>Fabrication, characterization, and modeling of metallic source/drain MOSFETs
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS).

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:15
Keyword
Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate, FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-49184 (URN)978-91-7501-161-5 (ISBN)
Public defence
2011-12-16, Sal / Hall C2, KTH-Electrum, Isafjordsgatan 26, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20111206Available from: 2011-12-06 Created: 2011-11-25 Last updated: 2011-12-06Bibliographically approved

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