Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
2010 (English)In: 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, 9-13 p.Conference paper (Refereed)
This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.
Place, publisher, year, edition, pages
2010. 9-13 p.
CMOS technology, Device design, Device performance, Future generations, Gate underlap, Low temperature processing, MOSFETs, Nano-scaling, Ni-silicide, Oxide thickness, Salicides, Schottky barriers, Schottky-barrier MOSFET, Schottky-barrier-height engineerings, Series resistances, Si films
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-14036ScopusID: 2-s2.0-77955183371ISBN: 978-142447201-7OAI: oai:DiVA.org:kth-14036DiVA: diva2:329226
2010 27th International Conference on Microelectronics, MIEL 2010; Nis; Serbia; 16 May 2010 through 19 May 2010
QC 201007082010-07-082010-07-082014-08-26Bibliographically approved