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Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
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2010 (English)In: 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, 9-13 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper provides an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results. The present work, together with the work of other groups in this field, places silicide MSD SB-MOSFETs as a competitive candidate for future generations of CMOS technology.

Place, publisher, year, edition, pages
2010. 9-13 p.
Keyword [en]
CMOS technology, Device design, Device performance, Future generations, Gate underlap, Low temperature processing, MOSFETs, Nano-scaling, Ni-silicide, Oxide thickness, Salicides, Schottky barriers, Schottky-barrier MOSFET, Schottky-barrier-height engineerings, Series resistances, Si films
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-14036Scopus ID: 2-s2.0-77955183371ISBN: 978-142447201-7 (print)OAI: oai:DiVA.org:kth-14036DiVA: diva2:329226
Conference
2010 27th International Conference on Microelectronics, MIEL 2010; Nis; Serbia; 16 May 2010 through 19 May 2010
Note

QC 20100708

Available from: 2010-07-08 Created: 2010-07-08 Last updated: 2014-08-26Bibliographically approved
In thesis
1. Integration of metallic source/drain contacts in MOSFET technology
Open this publication in new window or tab >>Integration of metallic source/drain contacts in MOSFET technology
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0~1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices.

First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification.

Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0~1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary morphological stability up to 800 oC when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability.

Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0~1) silicides SB-MOSFETs as a competitive candidate for future CMOS technology.

Place, publisher, year, edition, pages
Stockholm: KTH, 2010. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2010:06
Keyword
CMOS technology, MOSFET, Schottky barrier MOSFET, metallic source/drain, contact resistivity, NiSi, PtSi, SALICIDE, ultrathin silicide, FinFET
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-13136 (URN)978-91-7415-680-5 (ISBN)
Public defence
2010-06-18, Sal C1, KTH-Electrum 1, Isafjordsgatan 22, Kista, 15:28 (English)
Opponent
Supervisors
Projects
NEMO, NANOSIL, SINANO
Note
QC20100708Available from: 2010-05-31 Created: 2010-05-28 Last updated: 2010-07-08Bibliographically approved

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Hellström, Per-ErikMalm, B. Gunnar

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