Systematic design of a flash ADC for UWB applications
2007 (English)In: 8th International Symposium on Quality Electronic Design, ISQED 2007: San Jose, CA; 26 March 2007 through 28 March 2007, 2007, 108-112 p.Conference paper (Refereed)
This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder The flash ADC has been implemented in a 0.18 um CMOS process. Circuit level simulations show that the proposed architecture can achieve an SNDR of 25.3 dB, and an SFDR of 29.3 dB, with an input signal frequency of 330 MHz, at a sampling rate of 1.2 GSPS. The ADC core dissipates 130 mW from a 1.8 V supply.
Place, publisher, year, edition, pages
2007. 108-112 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-14264DOI: 10.1109/ISQED.2007.155ISI: 000246368000016ScopusID: 2-s2.0-34548138863ISBN: 978-0-7695-2795-6OAI: oai:DiVA.org:kth-14264DiVA: diva2:331975
QC 201007292010-07-292010-07-292013-01-29Bibliographically approved