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Systematic design of a flash ADC for UWB applications
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-3802-7834
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2007 (English)In: 8th International Symposium on Quality Electronic Design, ISQED 2007: San Jose, CA; 26 March 2007 through 28 March 2007, 2007, 108-112 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder The flash ADC has been implemented in a 0.18 um CMOS process. Circuit level simulations show that the proposed architecture can achieve an SNDR of 25.3 dB, and an SFDR of 29.3 dB, with an input signal frequency of 330 MHz, at a sampling rate of 1.2 GSPS. The ADC core dissipates 130 mW from a 1.8 V supply.

Place, publisher, year, edition, pages
2007. 108-112 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-14264DOI: 10.1109/ISQED.2007.155ISI: 000246368000016Scopus ID: 2-s2.0-34548138863ISBN: 978-0-7695-2795-6 (print)OAI: oai:DiVA.org:kth-14264DiVA: diva2:331975
Note
QC 20100729Available from: 2010-07-29 Created: 2010-07-29 Last updated: 2013-01-29Bibliographically approved
In thesis
1. Reconfigurable Analog to Digital Converters for Low Power Wireless Applications
Open this publication in new window or tab >>Reconfigurable Analog to Digital Converters for Low Power Wireless Applications
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The commercialization of Marconi’s radio transmission and reception, along with the development of integrated circuits in the 1960’s have facilitated many new consumer products for wireless communication, where the mobile phones or handsets are one. These handsets started out as a portable phone, mounted in cars, and have with time added additional services as Short Message Service, and have today become a media center with global positioning, and high-speed internet connection. This has been possible with the use of multistandard radios, that can receive and transmit information using many different wireless communication standards. Many of these handsets have one dedicated integrated radio chain for each communication standard used, which results in a large and expensive integrated circuit for these modern handsets. The challenge of today is to make modern handsets cheaper, smaller, and lower in power consumption. The power consumption is an issue of particular importance since the capacity of the available power sources do not increase with the demands of the handsets. One proposed method to do this is to move towards Software Defined Radio, where software of the handset control a single reconfigurable radio, and set which communication standard that the handset is to use. In this way, the handset can be reconfigured to communicate in the most power or data efficient way, depending on the choice of the user. The area of the Software Defined Radio receiver is also smaller than the parallel chains that are implemented today, which reduces the cost of production. The Software Defined Radio receiver is very challenging to design, since there is a large number of wireless communication standards, sometimes even within the same frequency bands. This make the reception of a weak desired signal difficult, when there may be a strong interferer in the same frequency band. A key component in the Software Defined Radio receiver is the Analog to Digital Converter. The development of new wireless communication standards requires higher performance of the Analog to Digital Converter in the receiver. This performance is hard to achieve, when the power consumption should be low, and the area should be small, especially in the modern integrated circuit technologies.

This thesis put the development of the communication industry into a historical perspective, and gives a review of the fundamental development of wireless communication applications. The fundamental concepts and implementations of Analog to Digital Converters for multistandard wireless receiver chains are also covered. Finally two case studies on the design of multistandard Analog to Digital Converters for Software Defined Radio applications are presented. These Analog to Digital Converters implement different methods of reconfiguration in order to comply with the requirements of the standards. The first case study is to the knowledge of the author the first reported reconfigurable Analog to Digital Converter for Wireless Personal Area Networks, that can be reconfigured from Bluetooth to the UWB communication standard. This is done by changing the architecture of the Analog to Digital Converter from Sigma Delta type to flash type. This reconfigurable Analog to Digital Converter is implemented at transistor level. The second case study investigates the limits of circuit level reconfigurability in an algorithmic Analog to Digital Converter. It is found that the requirements of two wireless communication standards can be covered with the use of smart circuit design techniques. The performance of this Analog to Digital Converter has been validated with experimental measurements.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. xvi, 135 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:04
Keyword
Integrated Circuits, Analog to Digital Converters, Wireless communication, Electronics Engineering, Electrical Engineering
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-4774 (URN)978-91-7178-932-7 (ISBN)
Public defence
2008-06-02, N1, Electrum 3, Isafjordsgatan 29, Kista, 15:00 (English)
Opponent
Supervisors
Note
QC 20100729Available from: 2008-05-27 Created: 2008-05-27 Last updated: 2010-07-29Bibliographically approved
2. All Digital Polar Transmitter Design for Software Defined Radio: Architecture and Low Power Circuit Implementation
Open this publication in new window or tab >>All Digital Polar Transmitter Design for Software Defined Radio: Architecture and Low Power Circuit Implementation
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The evolving wireless communication technology is aiming highdata rate, high mobility, long distance and at the meantime, co-existwith various different standards. This developing trend requires ahighly linear transceiver system and it causes the problem of lowefficiency due to the large crest factor of signals. On the other hand,with process scaling, digital blocks are occupying more functions andchip area than before, to fully utilize the digital process low poweradvantage and save design cost, hardware reuse is preferable. Theconcept of Software Defined Radio (SDR) is raised to make thesystem more adaptable to multiple communication standards withminimal hardware resources.

In this doctoral dissertation work, the software defined radioarchitecture especially the all-digital polar transmitter architecture isexplored. System level comparison on different transmitter topologiesis carried out in the first place. Direct conversion, out-phasing andpolar transmitter topologies are compared. Based on the system levelevaluation, a Lowpass Sigma Delta Modulation (LPSDM) digitalpolar transmitter is designed under 90nm CMOS process andpackaged in QFN32. 19.3% peak efficiency and 11.4dBm outputpower is measured under single 1.0V supply. The constellationmeasurement achieved 5.08% for 3pi/8PSK modulation and 7.01%for QAM16 modulation output. The measurement on the packagedtransmitter AM/AM and AM/PM also demonstrated the linearity andpower efficiency performance under low voltage environment. This verified the possibility for a fully SDR solution in the future.

As a specific application and genuine creation, the UHF RFIDstandard is mapped into digital polar transmitter architecture. System level simulation is performed and transient signal parameters areextracted. To prove the SDR possibility, the system is fully designedby VHDL language and downloaded into FPGA hardware with highspeed serial port. The measured results confirm the possibility of thedigital polar transmitter architecture potential in SDR systemrealization.

Based on the design and verification of two different systems, themethodology for digital implementation of linear transmitter systemis developed and the skill to carry out optimization and measurementis also possessed. In conclusion, the academic publication andverification proved the feasibility of digital polar transmitterapplication in linear system and point out the direction for a fullySDR realization.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xviii, 96, 13, 17 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 12:10
Keyword
Switching Power Amplifier, All Digital Polar Transmitter, Lowpass Sigma Delta Modulation, Software Defined Radio, RFID, H-Bridge Architecture, Resonating, Filter Matching Network.
National Category
Computer Systems
Research subject
SRA - ICT
Identifiers
urn:nbn:se:kth:diva-116861 (URN)978-91-7501-614-6 (ISBN)
Public defence
2013-02-22, Forum Sal-D, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Projects
iPack
Note

QC 20130129

Available from: 2013-01-29 Created: 2013-01-28 Last updated: 2013-01-29Bibliographically approved

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