Self-heating effects in a BiCMOS on SOI technology for RFIC applications
2005 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, Vol. 52, no 7, 1423-1428 p.Article in journal (Refereed) Published
Self-heating in a 0.25 mu m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In, the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.
Place, publisher, year, edition, pages
IEEE Press, 2005. Vol. 52, no 7, 1423-1428 p.
BiCMOS, electrothermal simulation, radio frequency integrated circuit (RFIC), self-heating, silicon-on-insulator (SOI), thermal resistance, bipolar-transistors, thermal-resistance, model
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-14865DOI: 10.1109/ted.2005.850634ISI: 000230123100020ScopusID: 2-s2.0-23944446689OAI: oai:DiVA.org:kth-14865DiVA: diva2:332906
QC 201005252010-08-052010-08-052014-02-19Bibliographically approved