A triple-mode sigma-delta modulator for multi-standard wireless radio receivers
2006 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 2, 113-124 p.Article in journal (Refereed) Published
A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN.
Place, publisher, year, edition, pages
2006. Vol. 47, no 2, 113-124 p.
analog-to-digital conversion, triple-mode, sigma-delta modulator, feedforward path, multi-standard, wireless radio receiver, adcs
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-15651DOI: 10.1007/s10470-006-3298-6ISI: 000237195100002ScopusID: 2-s2.0-33646590599OAI: oai:DiVA.org:kth-15651DiVA: diva2:333693
QC 201005252010-08-052010-08-052012-10-02Bibliographically approved