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Influence of SOI-generated stress on BiCMOS performance
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6459-749X
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2006 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 50, no 6, 935-942 p.Article in journal (Refereed) Published
Abstract [en]

Two BiCMOS processes were adapted for SOI and the performance of the bipolar devices was studied. Differences in electrical parameters were observed, in particular the current gain, which processing or doping profiles could not explain, but correlated with observed stress in transistors. Simulation of the process flow with stress included revealed that stress was generated to a higher degree in the SOI wafers in the presence of deep trench isolation (DTI). Theoretical estimations and electrical simulations with and without stress yielded results consistent with observed data. Thus, we conclude that the observed differences are caused by process-induced in-plane biaxial stress.

Place, publisher, year, edition, pages
2006. Vol. 50, no 6, 935-942 p.
Keyword [en]
BiCMOS, SOI, silicon-on-insulator, trench isolation, bipolar, device characteristics, strained si
National Category
Physical Sciences
URN: urn:nbn:se:kth:diva-15891DOI: 10.1016/j.sse.2006.04.034ISI: 000239499400008ScopusID: 2-s2.0-33745739579OAI: diva2:333933
QC 20100525 QC 20111004. Conference: International Semiconductor Device Research Symposium (ISDRS 2005). Washington, DC. DEC 07-09, 2005 Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2011-10-04Bibliographically approved

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Johansson, TedMalin, B. GunnarÖstling, Mikael
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