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Macro pore and pillar array formation in silicon by electrochemical etching
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-5260-5322
KTH, School of Information and Communication Technology (ICT), Material Physics, Semiconductor Materials, HMA.
2006 (English)In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T126, 72-76 p.Article in journal (Refereed) Published
Abstract [en]

Electrochemical etching may be used to form high aspect-ratio pores and pillars in silicon. Starting from lithographically patterned surfaces, regular arrays of macro pores or pillars can be fabricated. The pitch and pillar) pore size must then scale with the depletion width, in turn set by the material resistivity. We review various results where the achievable pore diameter ranges from 100 mu m for high resistivity material to the submicron range for highly doped wafers. At slightly higher current density and using different patterns, pillars or walls may be formed. The fabricated structures may be further processed and we demonstrate oxidation, uniform wall doping and finally, filling of the structures to result in functional materials. Applications include both optical, microelectronic, material and bio-applications.

Place, publisher, year, edition, pages
2006. Vol. T126, 72-76 p.
Keyword [en]
n-type silicon, porous silicon, fabrication
National Category
Physical Sciences
URN: urn:nbn:se:kth:diva-16276DOI: 10.1088/0031-8949/2006/T126/017ISI: 000246789700018ScopusID: 2-s2.0-42349094102OAI: diva2:334318
QC 20100525 QC 20110927. Conference: 21sth Nordic Semiconductor Meeting. Sundvolden, NORWAY. AUG 18-19, 2005 Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2012-03-19Bibliographically approved

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