Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits
2008 (English)In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, ISSN 1549-8328, Vol. 55, no 4, 1041-1054 p.Article in journal (Refereed) Published
This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
Place, publisher, year, edition, pages
2008. Vol. 55, no 4, 1041-1054 p.
inverter, NAND, nonoverlapping clock generation circuit (CGC), NOR, power-supply noise (PSN), substrate noise, timing jitter, phase noise, pll jitter, delay, oscillators, impact, model
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-17569DOI: 10.1109/tcsi.2008.916565ISI: 000256258400008ScopusID: 2-s2.0-44949167876OAI: oai:DiVA.org:kth-17569DiVA: diva2:335613
QC 201005252010-08-052010-08-052012-02-14Bibliographically approved