Modeling of on-chip bus switching current and its impact on noise in power supply grid
2008 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 16, no 6, 766-770 p.Article in journal (Refereed) Published
In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance-inductance-capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.
Place, publisher, year, edition, pages
2008. Vol. 16, no 6, 766-770 p.
bus, power supply noise, transmission line
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-17609DOI: 10.1109/tvlsi.2008.2000258ISI: 000256768000018ScopusID: 2-s2.0-44249096826OAI: oai:DiVA.org:kth-17609DiVA: diva2:335653
QC 201005252010-08-052010-08-052012-02-14Bibliographically approved