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Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2008 (English)In: Thin Solid Films, ISSN 0040-6090, E-ISSN 1879-2731, Vol. 517, no 1, 117-120 p.Article in journal (Refereed) Published
Abstract [en]

Today MOSFET devices are approaching gate lengths on the order of 10 nm. This sets extreme demands on gate patterning technique. This paper describes a side wall transfer lithography technique to pattern decananomeer MOSFETs or nanowires. A correlated line edge roughness leading to a very low line width roughness was demonstrated for the patterned gates. Moreover, the technology was shown to be robust and reproducible with high yield and uniformity suitable for mass fabrication. Finally, integration of the sidewall transfer lithography was performed in various novel MOSFET devices.

Place, publisher, year, edition, pages
2008. Vol. 517, no 1, 117-120 p.
Keyword [en]
MOSFET, Gate length, Lithography, technology
Identifiers
URN: urn:nbn:se:kth:diva-18035DOI: 10.1016/j.tsf.2008.08.134ISI: 000261510700033Scopus ID: 2-s2.0-54849406354OAI: oai:DiVA.org:kth-18035DiVA: diva2:336080
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2017-12-12Bibliographically approved

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Hellström, Per-Erik

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