Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2009 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 28, no 8, 1237-1250 p.Article in journal (Refereed) Published
Abstract [en]

Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to alternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20% of the design cycle influence up to 80% of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow.

Place, publisher, year, edition, pages
2009. Vol. 28, no 8, 1237-1250 p.
Keyword [en]
Die stacking, performance and cost tradeoffs, power consumption, system-in-package (SiP), system-on-chip (SoC), system-on-package (SoP), thermal analysis, wafer-level integration (WLI), 3-D integration, on-chip, global interconnects, length distribution, 3-d ics, vlsi, design, power, architectures, connectivity, repeaters
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-18629DOI: 10.1109/tcad.2009.2021734ISI: 000268281800011Scopus ID: 2-s2.0-68549115318OAI: oai:DiVA.org:kth-18629DiVA: diva2:336676
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2012-02-14Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Zheng, Li-RongTenhunen, Hannu
By organisation
VinnExcellence Center for Intelligence in Paper and Packaging, iPACKElectronic, Computer and Software Systems, ECSMicroelectronics and Information Technology, IMIT
In the same journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 51 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf