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Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-0525-8647
KTH, School of Electrical Engineering (EES), Microsystem Technology.
KTH, School of Electrical Engineering (EES), Microsystem Technology.ORCID iD: 0000-0002-9820-8728
KTH, School of Electrical Engineering (EES), Microsystem Technology.
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2009 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 154, no 1, 180-186 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes. e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.

Place, publisher, year, edition, pages
2009. Vol. 154, no 1, 180-186 p.
Keyword [en]
Adhesive wafer bonding, Nano-imprint resist, Polymer, 3D IC MEMS, integration, Silicon-on-integrated-circuit, SOIC, nanoimprint lithography, polymer deformation, arrays, thermosets, design, flow
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-18753DOI: 10.1016/j.sna.2009.07.009ISI: 000269771200028Scopus ID: 2-s2.0-68849118449OAI: oai:DiVA.org:kth-18753DiVA: diva2:336800
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2017-12-12Bibliographically approved
In thesis
1. Integration and Packaging Concepts for Infrared Bolometer Arrays 
Open this publication in new window or tab >>Integration and Packaging Concepts for Infrared Bolometer Arrays 
2009 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

 

Infrared (IR) imaging devices based on energy detection has shown a dramatic development in technology along with an impressive price reduction in recent years. However, for a low-end market as in automotive applications, the present cost of IR cameras is still the main obstacle to broadening their usage. Ongoing research has continuously reduced the system cost. Apart from decreasing the cost of infrared optics, there are other key issues to achieve acceptable system costs, including wafer-level vacuum packaging of the detectors, low vacuum level operation, and the use of standard materials in the detector fabrication. This thesis presents concepts for cost reduction of low-end IR cameras.

     The thesis presents a study of detector performance based on the thermal conductance design of the pixel. A circuit analog is introduced to analyze the basic thermal network effect from the surrounding environment on the conductance from the pixel to the environment. A 3D simulation model of the detector array conductance has been created in order to optimize the performance of the arrays while operated in low vacuum. In the model, Fourier's law of heat transfer is applied to determine the thermal conductance of a composite material pixel. The resulting thermal conductance is then used to predict the performance of the detector array in low vacuum.

     The investigations of resist as the intermediate bonding material for 3D array integration are also reported in the thesis. A study has been made of the nano-imprint resists series mr-I 9000 using a standard adhesive wafer bonding scheme for thermosetting adhesives. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer. The evaluation, including assessment of the bonding surface uniformity and planarizing ability of topographical surfaces, is used to demonstrate the suitability of this resist as sacrificial material for heterogeneous detector array integration.

     Moreover, the thesis presents research in wafer-level packaging performed by room temperature bonding. Sealing rings, used to create a cavity, are manufactured by electroplating. The cavity sealing is tested by liquid injection and by monitoring the deflection of the lid membrane of the cavities. A value for the membrane deflection is calculated to estimate the pressure inside the cavities.  

Place, publisher, year, edition, pages
Stockholm: KTH, 2009. 58 p.
Series
Trita-EE, ISSN 1653-5146 ; 2009:030
Keyword
Fabrication, Bonding, packaging, microbolometer, Thermal imaging.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-10690 (URN)978-91-7415-337-8 (ISBN)
Presentation
2009-06-05, Seminar room floor 5, Osquldas väg 10, Stockholm, 10:00 (English)
Opponent
Supervisors
Available from: 2009-09-08 Created: 2009-06-25 Last updated: 2010-10-07Bibliographically approved
2. Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
Open this publication in new window or tab >>Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding.

The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as monocrystalline silicon, for MEMS devices that are closely integrated on top of sensitive integrated circuits substrates. Monocrystalline silicon has excellent mechanical properties that are hard to achieve otherwise, and therefore it fits well in devices for adaptive optics and maskwriting applications where nanometer precision deflection requirements call for mechanically stable materials. However, the temperature sensitivity of the integrated circuits prohibits the use of monocrystalline silicon with conventional deposition and surface micromachining techniques. Here, heterogeneous 3-D integration by adhesive wafer-bonding is used to fabricate three different types of spatial light modulators, based on micromirror arrays made of monocrystalline silicon; micromirror arrays with vertically moving “piston-type” mirrors and with tilting mirrors made of one functional monocrystalline silicon layer, and vertically moving hidden-hinge micromirror arrays made of two functional monocrystalline silicon layers.

The second part of the thesis addresses the need for room-temperature packaging methods that allow the packaging of liquids or in general heat sensitive devices on wafer-level. A packaging method was developed that is based on a hybrid wafer-bonding approach, combining the compression bonding of gold gaskets with adhesive bonding. The packaging method is first demonstrated for the wafer-level encapsulation of liquids in reservoirs and then applied to packaging a dye-based photonic gas sensor.

 

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xi, 126 p.
Series
Trita-EES, 2013:031
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-125913 (URN)978-91-7501-843-0 (ISBN)
Public defence
2013-09-06, F3, Lindstedtsvägen 26, KTH, Stockholm, 14:14 (English)
Opponent
Supervisors
Note

QC 20130816

Available from: 2013-08-16 Created: 2013-08-16 Last updated: 2013-08-19Bibliographically approved
3. Heterogeneous material integration for MEMS
Open this publication in new window or tab >>Heterogeneous material integration for MEMS
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes heterogeneous integration methods for the fabrication of microelectromechanical systems (MEMS). Most MEMS devices reuse the fabrication techniques that are found in the microelectronics integrated circuit industry. This limits the selection of materials and processes that are feasible for the realization of MEMS devices. Heterogeneous integration methods, on the other hand, consist of the separate pre-fabrication of sub-components followed by an assembly step. The pre-fabrication of subcomponents opens up for a wider selection of fabrication technologies and thus potentially better performing and more optimized devices. The first part of the thesis is focused upon an adhesive wafer-level layer transfer method to fabricate resistive microbolometer-based long-wavelength infrared focal plane arrays. This is realized by a CMOS-compatible transfer of monocrystalline silicon with epitaxially grown silicon-germanium quantum wells. Heterogeneous transfer methods are also used for the realization of filtering devices, integration of distributed small dies onto larger wafer formats and to fabricate a graphene-based pressure sensor. The filtering devices consist of very fragile nano-porous membranes that with the presented dry adhesive methods can be transferred without clogging or breaking. Pick-and-place methods for the massive transfer of small dies between different wafer formats are limited by time and die size-considerations. Our presented solution solves these problems by expanding a die array on a flexible tape, followed by adhesive wafer bonding to a target wafer. Furthermore, a gauge pressure sensor is realized by transferring a graphene monolayer grown on a copper foil to a micromachined target wafer with a silicon oxide interface layer. This device is used to extract the gauge factor of graphene. Adhesive bonding is an enabling technology for the presented heterogeneous integration techniques. A blister test method together with an experimental setup to characterize the bond energies between adhesives and bonded substrates is also presented.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xii, 87 p.
Series
Trita-EE, ISSN 1653-5146 ; 2013:039
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-129185 (URN)
Public defence
2013-10-25, Kollegiesalen, Brinellvägen 8, KTH, Stockholm, 10:00 (English)
Opponent
Supervisors
Note

QC 20131003

Available from: 2013-10-03 Created: 2013-09-22 Last updated: 2013-10-04Bibliographically approved

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