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A comparison design of comb decimators for sigma-delta analog-to-digital converters
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2000 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 22, no 1, 51-60 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

Place, publisher, year, edition, pages
2000. Vol. 22, no 1, 51-60 p.
Keyword [en]
comb decimator, non-recursive algorithm, recursive algorithm, low power, high speed, sigma-delta A/D converters, filter, power
Identifiers
URN: urn:nbn:se:kth:diva-19464ISI: 000083299200007OAI: oai:DiVA.org:kth-19464DiVA: diva2:338156
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

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