Functional validation of mixed hardware/software systems based on specification, partitioning, and simulation of test cases
2000 (English)In: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 5, no 1, 83-113 p.Article in journal (Refereed) Published
Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.
Place, publisher, year, edition, pages
2000. Vol. 5, no 1, 83-113 p.
system validation, test case development, HW/SW codesign
IdentifiersURN: urn:nbn:se:kth:diva-19581ISI: 000085541500004OAI: oai:DiVA.org:kth-19581DiVA: diva2:338273
QC 201005252010-08-102010-08-10Bibliographically approved