A 3 V wideband CMOS switched-current A/D-converter suitable for time-interleaved operation
2000 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 2, 127-139 p.Article in journal (Refereed) Published
The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f(in) = 1.83 MHz, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5 dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 mu m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR greater than or equal to 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.
Place, publisher, year, edition, pages
2000. Vol. 23, no 2, 127-139 p.
A/D converters, switched-current circuits, low-voltage CMOS
IdentifiersURN: urn:nbn:se:kth:diva-19770ISI: 000087115800004OAI: oai:DiVA.org:kth-19770DiVA: diva2:338462
QC 201005252010-08-102010-08-10Bibliographically approved