Statistical design of low power square-law CMOS cells for high yield
2000 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 3, 237-248 p.Article in journal (Refereed) Published
A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.
Place, publisher, year, edition, pages
2000. Vol. 23, no 3, 237-248 p.
IdentifiersURN: urn:nbn:se:kth:diva-19841ISI: 000087705500006OAI: oai:DiVA.org:kth-19841DiVA: diva2:338533
QC 201005252010-08-102010-08-10Bibliographically approved