Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Low voltage high-speed CMOS square-law composite transistor cell
Show others and affiliations
2000 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, no 3, 347-349 p.Article in journal (Refereed) Published
Abstract [en]

A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

Place, publisher, year, edition, pages
2000. Vol. 25, no 3, 347-349 p.
Keyword [en]
analog signal processing, CMOS, low voltage, composite transistor, multiplier
Identifiers
URN: urn:nbn:se:kth:diva-20091ISI: 000089798800018OAI: oai:DiVA.org:kth-20091DiVA: diva2:338784
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

Open Access in DiVA

No full text

Search in DiVA

By author/editor
Ismail, Mohammed
In the same journal
Analog Integrated Circuits and Signal Processing

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 23 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf