Low voltage high-speed CMOS square-law composite transistor cell
2000 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, no 3, 347-349 p.Article in journal (Refereed) Published
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.
Place, publisher, year, edition, pages
2000. Vol. 25, no 3, 347-349 p.
analog signal processing, CMOS, low voltage, composite transistor, multiplier
IdentifiersURN: urn:nbn:se:kth:diva-20091ISI: 000089798800018OAI: oai:DiVA.org:kth-20091DiVA: diva2:338784
QC 201005252010-08-102010-08-10Bibliographically approved