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Easily testable multiple-valued logic circuits derived from Reed-Muller circuits
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-7382-9408
2000 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 49, no 11, 1285-1289 p.Article in journal (Refereed) Published
Abstract [en]

In 1972, Reddy showed that the binary circuits realizing Reed-Muller canonical form are easily testable. In this paper, we extend Reddy's result to multiple-valued logic circuits. employing more than two discrete levels of signal, The electronic fabrication of such circuits became feasible due to the recent advances in integrated circuit technology. We show that, in the multiple-valued case, several new phenomena occur which allow us to asymptotically reduce the upper bound on the number of tests required for fault detection, but make the generation of tests harder.

Place, publisher, year, edition, pages
2000. Vol. 49, no 11, 1285-1289 p.
Keyword [en]
multiple-valued function, Reed-Muller circuit, easily testable circuit, stuck-at fault, design
Identifiers
URN: urn:nbn:se:kth:diva-20167ISI: 000165353100011OAI: oai:DiVA.org:kth-20167DiVA: diva2:338860
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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Dubrova, Elena

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