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Single level integration packaging: Meeting the requirements of ultra high density and high frequency
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2000 (English)In: Journal of electronics manufacturing, ISSN 0960-3131, E-ISSN 2047-6078, Vol. 10, no 1, 59-67 p.Article in journal (Refereed) Published
Abstract [en]

The traditional electronic packaging hierarchies present ct bottleneck for increasing system speed and density. A revolutionary rethinking is therefore necessary which aims to integrate or eliminate the current packaging hierarchies towards single level hierarchy integration. In this paper, such a novel packaging scenario is introduced. Its technology concerns and electric performance are studied.

Place, publisher, year, edition, pages
2000. Vol. 10, no 1, 59-67 p.
Keyword [en]
on-chip interconnections
Identifiers
URN: urn:nbn:se:kth:diva-20434ISI: 000167437000004OAI: oai:DiVA.org:kth-20434DiVA: diva2:339129
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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