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Design and power optimization of high-speed pipeline ADC for wideband CDMA applications
2001 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, no 3, 229-238 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 mum standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.

Place, publisher, year, edition, pages
2001. Vol. 26, no 3, 229-238 p.
Keyword [en]
wideband CDMA, pipeline, A/D converter, switched-opamp, a/d converter, cmos, 10-b
Identifiers
URN: urn:nbn:se:kth:diva-20494ISI: 000167828100004OAI: oai:DiVA.org:kth-20494DiVA: diva2:339189
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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Ismail, Mohammed
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