Statistical design of the four-MOSFET structure
2001 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 1, 115-121 p.Article in journal (Refereed) Published
The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.
Place, publisher, year, edition, pages
2001. Vol. 28, no 1, 115-121 p.
analog MOS ICs, yield enhancement, statistical design, four-MOSFET structure, VLSI, cmos
IdentifiersURN: urn:nbn:se:kth:diva-20600ISI: 000168529900012OAI: oai:DiVA.org:kth-20600DiVA: diva2:339296
QC 201005252010-08-102010-08-10Bibliographically approved