Change search
ReferencesLink to record
Permanent link

Direct link
A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS
2001 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 2, 195-200 p.Article in journal (Refereed) Published
Abstract [en]

A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

Place, publisher, year, edition, pages
2001. Vol. 28, no 2, 195-200 p.
Keyword [en]
frequency synthesizer, phase locked loop, dual modulus prescaler
URN: urn:nbn:se:kth:diva-20703ISI: 000169206800007OAI: diva2:339399
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

Open Access in DiVA

No full text

Search in DiVA

By author/editor
Ismail, Mohammed
In the same journal
Analog Integrated Circuits and Signal Processing

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 30 hits
ReferencesLink to record
Permanent link

Direct link