Change search
ReferencesLink to record
Permanent link

Direct link
Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2001 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, E-ISSN 1557-9980, Vol. 24, no 3, 245-254 p.Article in journal (Refereed) Published
Abstract [en]

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0 +/- 5 %. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.

Place, publisher, year, edition, pages
2001. Vol. 24, no 3, 245-254 p.
Keyword [en]
distributed LRC networks, on-chip interconnection, on-chip power distribution, power grid simulation, signal and power integrity, simultaneous switching noise, ULSI circuits, packages, devices, design, driver
URN: urn:nbn:se:kth:diva-20844ISI: 000170224700003OAI: diva2:339541
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

Open Access in DiVA

No full text

Search in DiVA

By author/editor
Zheng, Li-RongTenhunen, Hannu
By organisation
Microelectronics and Information Technology, IMIT
In the same journal
IEEE Transactions on Advanced Packaging

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 22 hits
ReferencesLink to record
Permanent link

Direct link