Statistical design of a 10 bit current division network
2001 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 29, no 3, 221-229 p.Article in journal (Refereed) Published
The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.
Place, publisher, year, edition, pages
2001. Vol. 29, no 3, 221-229 p.
analog MOS ICs, yield enhancement, statistical design, 10 bit current division network
IdentifiersURN: urn:nbn:se:kth:diva-20906ISI: 000170648100007OAI: oai:DiVA.org:kth-20906DiVA: diva2:339603
QC 201005252010-08-102010-08-10Bibliographically approved