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Design and analysis of power integrity in deep submicron system-on-chip circuits
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2002 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 1, 15-29 p.Article in journal (Refereed) Published
Abstract [en]

This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.

Place, publisher, year, edition, pages
2002. Vol. 30, no 1, 15-29 p.
Keyword [en]
power distribution, signal integrity, deep submicron CMOS, system-on-chip, supply noise-analysis, interconnect
Identifiers
URN: urn:nbn:se:kth:diva-21002ISI: 000171485800003OAI: oai:DiVA.org:kth-21002DiVA: diva2:339699
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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