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56 Gbit/s analogue PLL for clock recovery
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2001 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 37, no 22, 1336-1338 p.Article in journal (Refereed) Published
Abstract [en]

A clock-recovery circuit is reported that employs a phase-locked. loop (PLL) at 56.88 Gbit/s. and is demonstrate by locking to a 28.44 GHz sinosoidal signal while two additional circuits with adapted on-chip passive components are locked to 29 and 39 Gbit/s pseudorandom bit sequences, To the knowledge of the authors, this is the First demonstration of an integrated PLL integrated circuit for clock recovery at a data rate well above 40 Gbit/s.

Place, publisher, year, edition, pages
2001. Vol. 37, no 22, 1336-1338 p.
Identifiers
URN: urn:nbn:se:kth:diva-21074ISI: 000171943100014OAI: oai:DiVA.org:kth-21074DiVA: diva2:339771
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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