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Compact low voltage four quadrant CMOS current multiplier
2001 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 37, no 24, 1428-1429 p.Article in journal (Refereed) Published
Abstract [en]

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 mum technology shows a linearity error lower than 0.9% for signal swings up to +/- 50 muA. The Circuit operates at a supply of +/- 1.5V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz.

Place, publisher, year, edition, pages
2001. Vol. 37, no 24, 1428-1429 p.
Keyword [en]
URN: urn:nbn:se:kth:diva-21171DOI: 10.1049/el:20010988ISI: 000172687000002OAI: diva2:339868
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

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Ismail, Mohammed
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