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A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers
2002 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 1, 27-37 p.Article in journal (Refereed) Published
Abstract [en]

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

Place, publisher, year, edition, pages
2002. Vol. 37, no 1, 27-37 p.
Keyword [en]
baseband chain, channel-select filter, multistandard wireless receivers, continuous-time filter, a/d converter, range
Identifiers
URN: urn:nbn:se:kth:diva-21215ISI: 000173019300004OAI: oai:DiVA.org:kth-21215DiVA: diva2:339912
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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