A 7 GHz 1.5-V dual-modulus prescaler in 0.18 mu m copper-CMOS technology
2002 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 1, 89-95 p.Article in journal (Refereed) Published
A dual-modulus prescaler using True-Single-Phase-Clock (TSPC) logic is implemented in a 0.18 mum copper CMOS technology. With careful design and optimization the prescaler is able to operate at frequency up to 7.14 GHz at 1.5 V supply voltage. The high-speed operation is attributed to the adoption of the TSPC dynamic logic, and the all copper interconnect CMOS process which has much less interconnect parasitics than conventional aluminum technology. The design facilitates the implementation of a fully integrated RF CMOS phase-locked loop for applications in the 5.8 GHz ISM band such as wireless LAN.
Place, publisher, year, edition, pages
2002. Vol. 32, no 1, 89-95 p.
dual-modulus prescaler, frequency divider, TSPC logic, PLL, CMOS, circuit technique, flip-flops, speed, optimization, cml, ecl
IdentifiersURN: urn:nbn:se:kth:diva-21654ISI: 000176500900011OAI: oai:DiVA.org:kth-21654DiVA: diva2:340352
QC 201005252010-08-102010-08-10Bibliographically approved