Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips
2003 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, 39-47 p.Article in journal (Refereed) Published
In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.
Place, publisher, year, edition, pages
GZ DORDRECHT: KLUWER ACADEMIC PUBL , 2003. Vol. 34, no 1, 39-47 p.
Condensed Matter Physics
IdentifiersURN: urn:nbn:se:kth:diva-22126DOI: 10.1023/A:1020334300576ISI: 000179895800005OAI: oai:DiVA.org:kth-22126DiVA: diva2:340824
19th IEEE NORCHIP Conference STOCKHOLM, SWEDEN, NOV 12-13, 2001
QC 201005252010-08-102010-08-102013-12-04Bibliographically approved