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Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2003 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, 39-47 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.

Place, publisher, year, edition, pages
GZ DORDRECHT: KLUWER ACADEMIC PUBL , 2003. Vol. 34, no 1, 39-47 p.
Keyword [en]
silicon
National Category
Condensed Matter Physics
Identifiers
URN: urn:nbn:se:kth:diva-22126DOI: 10.1023/A:1020334300576ISI: 000179895800005OAI: oai:DiVA.org:kth-22126DiVA: diva2:340824
Conference
19th IEEE NORCHIP Conference STOCKHOLM, SWEDEN, NOV 12-13, 2001
Note

QC 20100525

Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved
In thesis
1. System-on-package solutions for multi-band RF front end
Open this publication in new window or tab >>System-on-package solutions for multi-band RF front end
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization.

The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained.

Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. ix, 88 p.
Series
Trita-IMIT. LECS, ISSN 1651-4076 ; 2005:08
Keyword
chip-package co-design, multi-band radio, system-on-package
National Category
Condensed Matter Physics
Identifiers
urn:nbn:se:kth:diva-482 (URN)91-7178-187-0 (ISBN)
Public defence
2005-11-25, Sal D, KTH-Forum, 10:00
Opponent
Supervisors
Note
QC 20101005Available from: 2005-11-09 Created: 2005-11-09 Last updated: 2010-10-05Bibliographically approved

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