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2 GHz controllable power amplifier in standard CMOS process for short-range wireless applications
2002 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 149, no 06-maj, 363-368 p.Article in journal (Refereed) Published
Abstract [en]

The authors present the design and implementation of a broadband radiofrequency power amplifier in a standard CMOS technology for short-range wireless applications. The amplifier is implemented in a standard 0.35 mum triple metal CMOS process. The amplifier is capable of delivering a maximum output power of 16.6 dBm at 1.91 GHz, and of 16 dBm at 2 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 33%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. The level of output power can be controlled in 2 dB Steps using a number of parallel semi-cascode stages.

Place, publisher, year, edition, pages
2002. Vol. 149, no 06-maj, 363-368 p.
Keyword [en]
design
Identifiers
URN: urn:nbn:se:kth:diva-22226DOI: 10.1049/ip-cds:20020555ISI: 000180748900013OAI: oai:DiVA.org:kth-22226DiVA: diva2:340924
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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