Adaptive Miller capacitor multiplier for compact on-chip PLL filter
2003 (English)In: Electronics Letters, ISSN 0013-5194, E-ISSN 1350-911X, Vol. 39, no 1, 43-45 p.Article in journal (Refereed) Published
An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 mum standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption. The lock time is reduced by 36% due to the adaptive loop bandwidth control during PLL settling.
Place, publisher, year, edition, pages
2003. Vol. 39, no 1, 43-45 p.
IdentifiersURN: urn:nbn:se:kth:diva-22306DOI: 10.1049/el:20030086ISI: 000181461300029OAI: oai:DiVA.org:kth-22306DiVA: diva2:341004
QC 201005252010-08-102010-08-10Bibliographically approved