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Current mode, low-power, on-chip signaling in deep-submicron CMOS technology
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
2003 (English)In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, no 3, 397-406 p.Article in journal (Refereed) Published
Abstract [en]

qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.

Place, publisher, year, edition, pages
2003. Vol. 50, no 3, 397-406 p.
Keyword [en]
current-mode circuits, deep submicron, digital noise, interconnect modeling, low-power design, on-chip signaling, RLC wire, interconnect
Identifiers
URN: urn:nbn:se:kth:diva-22391DOI: 10.1109/tcsi.2003.808837ISI: 000182026800008OAI: oai:DiVA.org:kth-22391DiVA: diva2:341089
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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