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Maximizing throughput over parallel wire structures in the deep submicrometer regime
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2003 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 11, no 2, 224-243 p.Article in journal (Refereed) Published
Abstract [en]

In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in sub-micron technologies.

Place, publisher, year, edition, pages
2003. Vol. 11, no 2, 224-243 p.
Keyword [en]
bandwidth maximization, crosstalk, high performance, high-speed interconnect, interconnect delay, on-chip bus, repeater insertion, throughput maximization, wire optimization, vlsi circuits, delay, interconnect, capacitance, design, inductance, insertion
Identifiers
URN: urn:nbn:se:kth:diva-22667DOI: 10.1109/tvlsi.2003.810800ISI: 000184091000007OAI: oai:DiVA.org:kth-22667DiVA: diva2:341365
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10Bibliographically approved

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