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A second order multi-bit Sigma Delta modulator with single-bit feedback
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 1, 63-72 p.Article in journal (Refereed) Published
Abstract [en]

Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 mum CMOS process, achieving 82 dB dynamic range at OSR 128 and a peak SNDR of 73.1 dB.

Place, publisher, year, edition, pages
2004. Vol. 38, no 1, 63-72 p.
Keyword [en]
sigma, delta, scaling, SNDR, modulation, a/d converter, adc
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-22842DOI: 10.1023/A:1025806506952ISI: 000185570600008Scopus ID: 2-s2.0-0346502040OAI: oai:DiVA.org:kth-22842DiVA: diva2:341540
Note
QC 20100525 QC 20111020Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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