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System modeling and transformational design refinement in ForSyDe
KTH, Superseded Departments, Electronic Systems Design.ORCID iD: 0000-0003-4859-3100
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 23, no 1, 17-32 p.Article in journal (Refereed) Published
Abstract [en]

The scope, of the Formal System Design (ForSyDe) methodology is high-level modeling and refinement of systems-on-a-chip and embedded systems. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal design-transformation methods for a transparent refinement process of the system model into an implementation model that is optimized for synthesis. The main contribution of this paper is the ForSyDe modeling technique and the formal treatment of transformational design refinement. We introduce process constructors, that cleanly separate the computation part of a process from the synchronization and communication part. We develop the characteristic function for each process type and use it to define semantic preserving and design decision transformations. These transformations are characterized by name, the format of the original process network, the transformed process network, and a design implication. The implication expresses the relation between original and transformed process network by means of the characteristic function. The objective of the refinement process is a model that can be implemented cost efficiently. To this end, process constructors and processes have a hardware and software interpretation which shall facilitate accurate performance and cost estimations. In a study of a digital equalizer example, we illustrate the modeling and refinement process and focus in particular on refinement of the clock domain, communication refinement, and resource sharing.

Place, publisher, year, edition, pages
2004. Vol. 23, no 1, 17-32 p.
Keyword [en]
formal methods, hardware/software codesign, modeling, system-on-a-chip (SoC), synchronous data flow, programming language, computation, software
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-23045DOI: 10.1109/tcad.2003.819898ISI: 000187573200002Scopus ID: 2-s2.0-0347761332OAI: oai:DiVA.org:kth-23045DiVA: diva2:341743
Note

QC 20150721

Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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Sander, Ingo

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