Interconnect intellectual property for Network-on-Chip (NoC)
2004 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 50, no 2-3, 65-79 p.Article in journal (Refereed) Published
As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network on chip: an architecture for billion transistor era, in: Proceeding of the IEEE NorChip Conference, November 2000; Network on chip, in: Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm, June 2002]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. Within an IIP, the switch has the central function. Depending on the network core of the NoC, the switch will have different architectures and implementations. This paper first briefly introduces the concept of NoC. It then studies NoC from an interconnect point of view and makes projections on future NoC parameters. At last, the IIP and its components are described, the switch is studied in more detail and a time-space-time (TST) switch designed for a circuit switched time-division multiplexing (TDM) NoC is proposed. This switch supports multicast traffic and is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.
Place, publisher, year, edition, pages
2004. Vol. 50, no 2-3, 65-79 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-23253DOI: 10.1016/j.sysarc.2003.07.003ISI: 000220155400002ScopusID: 2-s2.0-1242309795OAI: oai:DiVA.org:kth-23253DiVA: diva2:341951
QC 20100525 QC 201110312010-08-102010-08-102012-02-14Bibliographically approved