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Analysis of clock jitter effects in wideband sigma-delta modulators for RF-applications
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Electronic Systems Design.
2004 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, 223-236 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (SigmaDelta) Analog-to-Digital Converter ( ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that it is stochastic white Gaussian noise. Using this assumption, the SigmaDelta performance is characterized in terms of Signal-to-Jitter-Noise-Ratio (SJNR) for each jitter effect. Non-uniform sampling effects have, to some extent, been characterized in litterature ( S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters - Theory, Design and Simulation, IEEE Press, NewJersey, 1997). However, varying phase-length effects are also a main focus in this work since they can have a significant impact on the total ADC performance depending on settling accuracy and characteristic. Furthermore, because SC circuits usually operate on a two-phase clock, jitter may give rise to a secondary effect, phase overlap, which does not appear when dealing with a single-phase clock. This effect severely degrades the resolution of a SigmaDelta and therefore a thorough understanding of the interaction of jitter on the two phases is necessary.

Place, publisher, year, edition, pages
2004. Vol. 41, no 03-feb, 223-236 p.
Keyword [en]
clock jitter, wideband sigma-delta, delta-sigma, CMOS, RF-applications, switched-capacitor, jitter, sampling, sigma-delta
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-23728DOI: 10.1023/B:ALOG.0000041638.12447.7dISI: 000223914200012Scopus ID: 2-s2.0-4544383631OAI: oai:DiVA.org:kth-23728DiVA: diva2:342427
Note

QC 20100525 QC 20110923. 9th IEEE International Conference on Electronics, Circuits and Systems. DUBROVNIK, CROATIA. SEP 15-18, 2002

Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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